1. Field of the Invention
The invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a micro-trench storage capacitor.
2. Description of the Related Art
Recently, requirement for improvement in a high density integration of large scale integrated circuits has been on the increase thereby a minimization in size of each element constituting the large scale integrated circuits is also required. The large scale integrated circuits generally include dynamic random access memories involving many capacitors. To obtain a further improvement in a high density integration of the large scale integrated circuit, a further minimization in size of the storage capacitors constituting memory devices is required.
On the other hand, the storage capacitor is of course required to have a necessary capacity. As well known, the capacity of the capacitor depends upon a contact area between electrode and dielectric film constituting the capacitor. A large contact area between the electrode and the dielectric film provides the capacitor with a large capacity.
To realize a further improvement in a high density in integration of the large scale integrated circuits involving the storage capacitors, each of the storage capacitors is required to have a possible small occupied area and a possible large contact surface between electrode and dielectric film involved in the capacitor. For that purpose, various capacitor structures have been proposed.
One of conventional structures of the capacitors is disclosed in the Japanese patent application No. 2-327069 in which a hemispheric grain polysilicon is used as a bottom electrode to allow the capacitor to have a large storage capacitor in a limited small occupied area.
Another of the conventional structures of the capacitors is disclosed in the Japanese laid-open patent application No. 3-139882 in which a polysilicon film with a high impurity concentration of phosphorus is formed on a high melting point siliside to be etched by a hot phosphorus etchant to form unevenness on a surface of the polysilicon film to enlarge a surface area thereof.
Still another of the conventional structures of the capacitors is disclosed in 1992 December, Proceeding of the 43rd Symposium on Semiconductors and Integrated Circuits Technology, pp. 126-131 in which a micro-trench storage capacitor was proposed. Fabrication processes of this conventional capacitor will be described in detail with reference to FIGS. 1A to 1C.
With reference to FIG. 1A, an isolation silicon oxide film 102 is formed on a surface of a silicon substrate 101. A silicon nitride film 103 is deposited on a surface of the isolation oxide film 102 by use of a chemical vapor deposition method. A silicon oxide film 104 is further deposited on a surface of the silicon nitride film 103 by use of a chemical vapor deposition method. A contact hole is formed by use of both lithography and etching to penetrate through the triplet films or the silicon oxide and silicon nitride films 102, 103 and 104 until a part of the surface of the silicon substrate 101 is exposed through the contact hole. A chemical vapor deposition is subsequently carried out to deposit a polysilicon film 106 having a thickness of 400 nanometers on a top surface of the silicon oxide film 104 to thereby fill the contact hole with the polysilicon. The polysilicon film is subjected to an introduction of phosphorus by use of diffusion. A silicon oxide film 107 having a thickness of 20 nanometers is deposited on a top surface of the phosphorus-doped polysilicon film 106 by use of a chemical vapor deposition. The polysilicon film 106 and the silicon oxide film 107 are then defined by lithography and etching processes thereby the remaining part of the polysilicon film serves as a bottom electrode. Hemispherical grains 108 of silicon are formed by use of a chemical vapor deposition method and subsequent annealing process, if any, on a top surface of the silicon oxide film 107, exposed side walls of the polysilicon film 106 and the top surface of the silicon oxide film 107.
With reference to FIG. 1B, the silicon oxide film 107 is subjected to a dry etching using the hemispherical grains 108 as masks so that the silicon oxide film 107 partially remains only under the hemispherical grains 108.
With reference to FIG. 1C, the polysilicon film 106 serving as the bottom electrode is subjected to a dry etching using the remaining silicon oxide film 107 as a mask to form trench grooves 106a under apertures of the remaining silicon oxide film 107 so that the bottom electrode has alternate trench grooves 106a and trench pillars.
With reference to FIG. 1D, the silicon oxide films 107 and 104 are etched by use of a fluorate etchant. A dielectric film 109 is formed on an entire surface of the bottom electrode with the trench grooves and the trench pillars. A polysilicon film 110 is deposited on the dielectric film 109 of an introduction of phosphorus and subsequent lithography and etching processes to define a top electrode of the polysilicon film 110. This results in a completion of the formation of the micro-trench storage capacitor.
The micro-trench structure comprising the alternate trench pillars and trench grooves enlarges the contact surface between the dielectric film and either of the top and bottom electrodes. Namely, the micro-trench structure comprising the alternate trench pillars and trench grooves allows the storage capacitor to have a sufficiently large capacity and a small occupied area for implementation of a high integration of the storage capacitors.
The above conventional fabrication methods for the microtrench storage capacitors is, however, engaged with problems as the hemispherical grains were used as mask to form the microtrench grooves. It is difficult to control the grain size which defines the size of the micro-trench pillars and apertures. To grow the grain, a clean silicon surface is also required, although it is difficult to keep the required clean surface of the silicon. It is further required to keep a clean atmosphere in a chamber involved in the heat treatment system, although it is difficult to keep the required clean atmosphere. Those constraints result in a lowering of an efficiency in manufacturing of the storage capacitors.
It is therefore required to develop a novel fabrication method for the required storage capacitor without use of any growth of crystal grain or application of the material for the mask on the substrate.